The project “Automatic Digital Examiner” is basically an effort of digital design using VHDL and prototyping in FPGA. The project aims to build an optical mark reader which will be used to check the multiple answer answers sheets. As the manual checking of the huge number of multiple answer sheets is tedious, inefficient and time consuming a demand of device exists which can fulfill the purpose efficiently, reliably and promptly. The project is built as an alternative to commonly used scanning – image processing method of objective answer sheet checking. Apart from the trivial part of comparison of actual processing results and correct results, the project is completely realized in hardware by synthesizing digital circuits in Spartan 3E FPGA. A sensor module is used to get analog voltages corresponding to dark/light marks or no mark in the answer sheet. Before they are compared directly, certain algorithms of processing are implemented in FPGA after digitization. A major effort was made in this project also to generate simple and effective algorithms to attain the best results after processing. Finally attempts have also been made to store the processed results in a computer and construct a GUI to manage the stored outputs systematically. The basic elements integrated in the system are optical sensor array, ADC, FPGA, including RS232C interface with computer


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